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Gu¨rol Saglam
Digital Design/FPGA/ASIC Engineer
Address:
Karlsruhe, Germany
Google Scholar:
EDUCATION
M.Sc. Computer Science — Ozyegin University — 3.87/4 GPA
Sept 2019 - Sept 2022
• Topic: FPGA Implementation of High-Bandwidth Communication through LED-Based DCO-OFDM
B.Sc. Electrical and Electronics Engineering — Ozyegin University — 3.29/4 GPA
Sept 2015 - June 2019
• Focus: Electronics and Digital Systems
• Ranked 1st in the Electrical & Electronics Engineering Department in the class of 2019
Minor Computer Science — Ozyegin University — 3.20/4 GPA
Feb 2018 - June 2019
• Focus: Object Oriented Programming, Data Structures and Algorithms
EXPERIENCE
Researcher, Digital Design Engineer — CDNC, Karlsruhe Institute of Technology
Dec 2022 - June 2025
• Conducted in-depth research on digital logic design for Printed Electronics (PE) utilizing Synopsys and ModelSim
• Actualized and optimized hardware for machine learning (ML) models to effectively address PE constraints
• Created testbenches for verification and performed Static Timing Analysis (STA) following the ASIC Design Flow
• Delivered automated frameworks in Python for ALU approximation using a genetic algorithm
• Streamlined the training of machine learning models for bespoke approximate digital designs
• Built a Python RISCV Assembly Generator for ML models, improving memory usage, callbacks, and branches
• Instructed students on SoC design and AMD’s Xilinx Vivado Suite twice
• Constructed a new curriculum for the FPGA Programming lab
• Supervised 2 software development projects in Praxis der Software-Entwicklung (PSE), mentored 10 students
Researcher, FPGA Engineer — nEMESysLab, Ozyegin University
Sept 2019 - Nov 2022
• Executed in-depth research on SoC/FPGA design utilizing Quartus Prime and ModelSim
• Designed RTL for DCO-OFDM, enhancing high-bandwidth communication in the Visible Light Spectrum
• Provided tools for auto-generating parameterizable designs, streamlining the design process
• Carried out rigorous debugging on real hardware, identifying and resolving hardware-related issues to ensure
optimal performance and functionality
• Instructed students on Computer Architecture, FPGA design, and AMD’s Xilinx ISE Design Suite seven times
• Coordinated the work of up to 5 other TAs and managed labs for up to 150 students, improved leadership skills
Researcher — nEMESysLab, Ozyegin University
June 2018 - Sept 2018
• Conducted research in the Quartus Prime environment for Intel Altera FPGAs, focusing on tool evaluation
• Designed custom digital logic circuits to test the functionality of various tools effectively
• Authored comprehensive reports and guides for each tool, ensuring future usability and reference
Software Testing Intern — Kariyer.net
July 2017 - Aug 2017
• Executed manual testing to ensure software quality and functionality
• Received comprehensive training in automated testing techniques to enhance testing efficiency
• Gained proficiency in Agile methodologies, TestRail, and Jira for effective project management
• Leveraged Selenium and Appium frameworks to improve mobile and web-based testing processes
SKILLS
Software
Languages & HDL
Verilog HDL
VHDL
Python
Perl
C/C++
Tcl
Java/Javascript
Matlab
LANGUAGES
Turkish (Native)
English (C2)
German (B1)
PUBLICATIONS
• G.Saglam, F.Afentaki, G.Zervakis, M.B.Tahoori, Sequential Printed MLP Circuits for Super TinyML Multi-Sensory
Applications, 30th Asia and South Pacific Design Automation Conference (ASPDAC), ACM, Jan, 2025.
• P.Pal, F.Afentaki, H.Zhao, G.Saglam, M.Hefenbrock, G.Zervakis, M.Beigl, M.B.Tahoori, Fault Sensitivity Analysis
of Printed Bespoke MLP Classifiers, 2024 IEEE European Test Symposium (ETS), IEEE, May, 2024.
• F.Afentaki, G.Saglam, A.Kokkinis, K.Siozios, G.Zervakis, M.B.Tahoori, Bespoke Approximation of
Multiplication-Accumulation & Activation Targeting Printed MLPs, 2023 IEEE/ACM International Conference on
Computer Aided Design (ICCAD), IEEE, Nov, 2023.
• V.E.Levent, G.Saglam, H.F.Ugurdag, N.F.R.Annafianto, F.Aydin, S.W.Tesfay, B.Aly, M.Elamassie, B.Kebapci,
M.Uysal, FPGA Based DCO-OFDM PHY Transceiver for VLC Systems, 11th International Conference on
Electrical and Electronics Engineering (ELECO), IEEE, Nov, 2019.
• A.Varici, G.Saglam, S.Ipek, A.Yildiz, S.Goren, A.Aysu, D.Iskender, T.B.Aktemur, H.F.Ugurdag, Fast and Efficient
Implementation of Lightweight Crypto Algorithm PRESENT on FPGA through Processor Instruction Set Extension,
IEEE East-West Design & Test Symposium (EWDTS), IEEE, Sep 2019.
PROJECTS
FPGA Implementation of OFDM based VLC — M. Sc. Thesis
• Implemented DC Biased Optical OFDM (DCO-OFDM) for a Visible Light Communication System on FPGA,
adapting the RF methodology of OFDM to enable transmission through light sources such as LEDs
• Addressed the high complexity of DCO-OFDM calculations by leveraging FPGA technology, effectively meeting
the growing demand for higher bandwidth in communication systems
• Supplied testbenches for each module for verification, ensuring functionality
• Used Matlab for input and expected output generation during verification
Synthesis of Customized Processors for Specific Software Tasks — B. Sc. Thesis
• Developed a comprehensive tool in Python/Perl/Tcl for customization of the Very Simple CPU, translating
compiled assembly code into tailored memory implementations and a customized soft core in Verilog HDL
• Deployed debugging capabilities with command-line simulation
• Assembled a Tcl script for synthesis, place-and-route and bitstream generation as a Xilinx project
VSCPU Simulator
• Delivered an Instruction Set Architecture (ISA) simulator in Java for Very Simple CPU
• Applied Software Design Patterns (Singletons, Mediators...) using Advanced OOP, available on GitHub
OzU Rover Team
• Manufactured rover prototypes in a student-driven, multi-disciplinary research team at Ozyegin University
• Designed PCB layouts for all components, worked on communication using UART, SPI, I2C, ROS
• Competed in European Rover Challenge, mentored the team the following year, available on our website
Voice-Controlled Chess
• Built a voice-controlled chess game using the SpeechRecognition library and Google API
• Utilized tkinter from Python’s Standard Library to construct the front-end
Kariyer.net Mobile Testing Automation
• Proposed tool comparing job listings in web and mobile apps, identifying inconsistencies in API results
• Identified opportunities to reduce fixed costs and human error in manual testing, available on GitHub
Study Room Counter
• Engineered a cost-effective solution for tracking room occupation to automate booking within the campus network
REFERENCES
Available upon request.